Firmware

Design

The firmware for the designs were written in VHDL. The architecture was written using RTL, Register Transfer Level, designs.

Test benches

The test benches to verify the RTL designs were written using Verilog.

Block diagram

WAVEFORMS

Clock Divide Testbench

This waveform shows the two clock inputs, labeled SYS_CLK (100 MHz) and ADC_CLK (80 MHz), and the clock outputs. This block divides 100 MHz down to 50 MHz, 400 KHz, and 100 KHz. The 80 MHz clock is not used in the dividing so it can be an arbitrary speed in this test.

Display Testbench

This testbench verifies the user input is appropriately managed by the Display Module and outputs to the four-digit seven-seg display.

Mic Module to ADC Testbench

This testbench verifies the I2C protocol between the microphone module and the external ADC.

SPKR_I2C Testbench

This testbench verifies the I2C protocol between the speaker module and the DAC on the PCB.

Watters Engineering

Maria Watters

FIRMware

Block diagram

WAVEFORMS